Struct Spi 

pub struct Spi<SPIX, SCK, MISO, MOSI, WORD = Byte> { /* private fields */ }

A configured SPI master, owning the peripheral and its three pins.

WORD is the frame width: transfer_byte and SpiBus<u8> live on Spi<.., Byte>, transfer_word and SpiBus<u16> on Spi<.., Word>. Defaults to Byte.

Chip select is not handled here — NSS is software-managed, so drive the slave’s CS with an ordinary output pin around each transaction.

Implementations

impl<SPIX, SCK, MISO, MOSI> Spi<SPIX, SCK, MISO, MOSI, Byte>

where SPIX: Instance, SCK: SckPin<SPIX>, MISO: MisoPin<SPIX>, MOSI: MosiPin<SPIX>,

pub fn new( rcu: &mut Rcu, spi: SPIX, sck_pin: SCK, miso_pin: MISO, mosi_pin: MOSI, config: SpiConfig, ) -> Self

Enables the peripheral’s clock, resets it and configures 8-bit master mode.

The pins must already be in this SPI’s alternate function; release hands them back.

impl<SPIX, SCK, MISO, MOSI> Spi<SPIX, SCK, MISO, MOSI, Word>

where SPIX: Instance, SCK: SckPin<SPIX>, MISO: MisoPin<SPIX>, MOSI: MosiPin<SPIX>,

pub fn new_word( rcu: &mut Rcu, spi: SPIX, sck_pin: SCK, miso_pin: MISO, mosi_pin: MOSI, config: SpiConfig, ) -> Self

Same as new, but configures 16-bit frames.

impl<SPIX, SCK, MISO, MOSI, WORD> Spi<SPIX, SCK, MISO, MOSI, WORD>

where SPIX: Instance,

pub fn read_ready(&self) -> bool

Returns whether a received word is waiting in DATA (RBNE).

Only guarantees that the next single read will not block.

pub fn write_ready(&self) -> bool

Returns whether DATA can accept the next word (TBE).

True at idle, the bus having nothing queued; it says nothing about a word still on its way back.

pub fn take_error(&mut self) -> Option<Error>

Returns the pending error, if any, and clears it.

The acknowledge for Event::Error: those flags are what hold the interrupt request up, so a handler that skips this re-enters forever. One error per call — with two pending, the second survives for the next. Overrun also needs DATA drained, which the read a handler makes to do its work already does.

pub fn listen(&mut self, event: Event)

Raises an interrupt on event, which still has to be unmasked in the NVIC.

Event::Tbe is true whenever nothing is queued, so a handler that listens for it must call unlisten once it has nothing left to send.

pub fn unlisten(&mut self, event: Event)

Stops raising an interrupt on event.

pub fn is_listening(&self, event: Event) -> bool

Whether event is being listened for.

pub fn release(self, rcu: &mut Rcu) -> (SPIX, SCK, MISO, MOSI)

Waits for the last word to leave the wire, then returns the peripheral and the three pins, disabled, with its interrupts off and its clock stopped. A received word not yet read is discarded.

impl<SPIX, SCK, MISO, MOSI> Spi<SPIX, SCK, MISO, MOSI, Byte>

where SPIX: Instance,

pub fn write_byte(&mut self, byte: u8)

Hands one byte to DATA and returns at once, the clock now running.

Half an exchange: the answer arrives eight clocks later, on Event::Rbne. Check write_ready first — writing over a full transmit buffer loses the byte.

pub fn read_byte(&mut self) -> u8

Takes the byte that arrived on MISO, clearing RBNE.

The other half: meaningful only once read_ready holds, and it reports no error — take_error drains those.

pub fn transfer_byte(&mut self, byte: u8) -> Result<u8, Error>

Exchanges one byte: sends byte on MOSI and returns what arrived on MISO.

Blocks until the exchange has completed, so nothing is left pending on the bus when it returns.

Errors

The error take_error finds once the exchange is over; the received byte is then discarded.

pub fn transfer_bytes( &mut self, read: &mut [u8], write: &[u8], ) -> Result<(), Error>

Exchanges two buffers: byte i of write goes out and what comes back lands at byte i of read.

Errors

The first failed exchange, as in transfer_byte; the bytes after it are neither sent nor received.

Panics

If the lengths differ. To read more than is written, pad write — fill names the usual levels.

pub fn transfer_bytes_in_place(&mut self, words: &mut [u8]) -> Result<(), Error>

Exchanges words against itself: each byte is replaced by what came back.

Errors

The first failed exchange, as in transfer_byte; the bytes after it are neither sent nor received.

impl<SPIX, SCK, MISO, MOSI> Spi<SPIX, SCK, MISO, MOSI, Word>

where SPIX: Instance,

pub fn write_word(&mut self, word: u16)

Hands one 16-bit word to DATA and returns at once, the clock now running.

Half an exchange: the answer arrives sixteen clocks later, on Event::Rbne. Check write_ready first — writing over a full transmit buffer loses the word.

pub fn read_word(&mut self) -> u16

Takes the word that arrived on MISO, clearing RBNE.

The other half: meaningful only once read_ready holds, and it reports no error — take_error drains those.

pub fn transfer_word(&mut self, word: u16) -> Result<u16, Error>

Exchanges one 16-bit word: sends word on MOSI, returns what arrived on MISO.

Blocks until the exchange has completed, so nothing is left pending on the bus when it returns.

Errors

The error take_error finds once the exchange is over; the received word is then discarded.

pub fn transfer_words( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), Error>

Exchanges two buffers: word i of write goes out and what comes back lands at word i of read.

Errors

The first failed exchange, as in transfer_word; the words after it are neither sent nor received.

Panics

If the lengths differ. To read more than is written, pad write — fill names the usual levels.

pub fn transfer_words_in_place( &mut self, words: &mut [u16], ) -> Result<(), Error>

Exchanges words against itself: each word is replaced by what came back.

Errors

The first failed exchange, as in transfer_word; the words after it are neither sent nor received.

Trait Implementations

impl<SCK, MISO, MOSI> DmaDst<2> for Spi<Spi0, SCK, MISO, MOSI, Byte>

impl<SCK, MISO, MOSI> DmaDst<2> for Spi<Spi0, SCK, MISO, MOSI, Word>

impl<SCK, MISO, MOSI> DmaDst<4> for Spi<Spi1, SCK, MISO, MOSI, Byte>

impl<SCK, MISO, MOSI> DmaDst<4> for Spi<Spi1, SCK, MISO, MOSI, Word>

impl<SCK, MISO, MOSI> DmaPeriph<1> for Spi<Spi0, SCK, MISO, MOSI, Byte>

type Word = u8

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaPeriph<1> for Spi<Spi0, SCK, MISO, MOSI, Word>

type Word = u16

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaPeriph<2> for Spi<Spi0, SCK, MISO, MOSI, Byte>

type Word = u8

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaPeriph<2> for Spi<Spi0, SCK, MISO, MOSI, Word>

type Word = u16

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaPeriph<3> for Spi<Spi1, SCK, MISO, MOSI, Byte>

type Word = u8

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaPeriph<3> for Spi<Spi1, SCK, MISO, MOSI, Word>

type Word = u16

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaPeriph<4> for Spi<Spi1, SCK, MISO, MOSI, Byte>

type Word = u8

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaPeriph<4> for Spi<Spi1, SCK, MISO, MOSI, Word>

type Word = u16

The word type this peripheral transfers, fixing PWIDTH/MWIDTH.

fn addr(&self) -> u32

Address of the peripheral’s data register.

fn enable_dma(&mut self)

Lets the peripheral raise DMA requests on its channel.

fn disable_dma(&mut self)

Stops the peripheral raising DMA requests.

impl<SCK, MISO, MOSI> DmaSrc<1> for Spi<Spi0, SCK, MISO, MOSI, Byte>

impl<SCK, MISO, MOSI> DmaSrc<1> for Spi<Spi0, SCK, MISO, MOSI, Word>

impl<SCK, MISO, MOSI> DmaSrc<3> for Spi<Spi1, SCK, MISO, MOSI, Byte>

impl<SCK, MISO, MOSI> DmaSrc<3> for Spi<Spi1, SCK, MISO, MOSI, Word>

impl<SPIX, SCK, MISO, MOSI, WORD> ErrorType for Spi<SPIX, SCK, MISO, MOSI, WORD>

where SPIX: Instance,

type Error = Error

Error type.

impl<SPIX, SCK, MISO, MOSI> SpiBus for Spi<SPIX, SCK, MISO, MOSI, Byte>

where SPIX: Instance,

fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), Self::Error>

Wait until all operations have completed and the bus is idle.

fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error>

Read words from the slave.

fn write(&mut self, words: &[u8]) -> Result<(), Self::Error>

Write words to the slave, ignoring all the incoming words.

impl<SPIX, SCK, MISO, MOSI> SpiBus<u16> for Spi<SPIX, SCK, MISO, MOSI, Word>

where SPIX: Instance,

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), Self::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place(&mut self, words: &mut [u16]) -> Result<(), Self::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), Self::Error>

Wait until all operations have completed and the bus is idle.

fn read(&mut self, words: &mut [u16]) -> Result<(), Self::Error>

Read words from the slave.

fn write(&mut self, words: &[u16]) -> Result<(), Self::Error>

Write words to the slave, ignoring all the incoming words.