Module fmc 

Flash memory controller.

The wait states are not set from here: they have to be raised before the system clock speeds up, so UnfrozenRcu::freeze borrows this type and writes them itself.

Erasing and programming need CTL unlocked, which happens for the body of Fmc::with_unlocked and no longer. The option bytes are covered too, as a block: OptionBytes is read, changed and written back whole, because erasing them takes every byte at once. A written block only takes effect on the next load, Fmc::reload_option_bytes or a power-up.

let mut fmc = dp.fmc.constrain();
let config = ClockConfig::default().sysclk(SysClk::Pll(PllFreq::Mhz48));
let mut rcu = dp.rcu.constrain().freeze(&mut fmc, config);

fmc.with_unlocked(|f| {
    f.erase_page(Page::P63)?;
    f.program(Page::P63, 0, 0xDEAD_BEEF)
})?;

Structs

Fmc

Owns the flash memory controller.

OptionBytes

The option byte block as a whole, read with Fmc::read_option_bytes and written back with UnlockedFmc::write_option_bytes.

UnlockedFmc

The flash controller with CTL unlocked, borrowed for the body of Fmc::with_unlocked and locked again when that call returns.

Enums

Boot1

The level BOOT1 is taken to have (BOOT1_n, stored inverted).

Error

What an erase or a program operation failed on.

Event

An FMC event that can raise an interrupt.

FreeWatchdog

Which free watchdog the part starts with (nWDG_SW).

LowPowerEntry

What entering deep-sleep or standby does (nRST_DPSLP, nRST_STDBY).

Page

An erasable 1 KB page of the main flash.

ProtectionLevel

How far the option bytes lock the flash against being read out.

SramParity

Whether the SRAM parity check is on (SRAM_PARITY_CHECK, stored inverted).

VddaMonitor

Whether the supply monitor watches VDDA (VDDA_VISOR).

Traits

FmcExt

Entry point on the raw peripheral.