gd32e2_hal/watchdog.rs
1//! The chip's two watchdogs.
2//!
3//! Both reset the chip unless fed in time, and neither can be stopped once
4//! started. What separates them is what they can catch:
5//!
6//! - [`Fwdgt`] runs off IRC40K, independent of the system clock, and spans
7//! milliseconds to 26 seconds. It notices that code stopped feeding it —
8//! nothing more.
9//! - [`Wwdgt`] runs off `PCLK1` and spans tens of milliseconds. Feeding it too
10//! early is a fault as well, so it also notices code that kept running but
11//! lost its pace, and it can raise an interrupt one tick before the reset.
12//!
13//! A watchdog that has to survive a broken clock tree is [`Fwdgt`]; one that
14//! checks the rhythm of a tight control loop is [`Wwdgt`].
15//!
16//! ```ignore
17//! let mut watchdog = dp.fwdgt.constrain(&mut rcu).start_timeout(2.secs());
18//! loop {
19//! watchdog.feed();
20//! }
21//! ```
22
23mod fwdgt;
24mod wwdgt;
25
26pub use fwdgt::*;
27pub use wwdgt::*;