Module watchdog 

The chip’s two watchdogs.

Both reset the chip unless fed in time, and neither can be stopped once started. What separates them is what they can catch:

• Fwdgt runs off IRC40K, independent of the system clock, and spans milliseconds to 26 seconds. It notices that code stopped feeding it — nothing more.
• Wwdgt runs off PCLK1 and spans tens of milliseconds. Feeding it too early is a fault as well, so it also notices code that kept running but lost its pace, and it can raise an interrupt one tick before the reset.

A watchdog that has to survive a broken clock tree is Fwdgt; one that checks the rhythm of a tight control loop is Wwdgt.

let mut watchdog = dp.fwdgt.constrain(&mut rcu).start_timeout(2.secs());
loop {
    watchdog.feed();
}

Structs

Fwdgt

The watchdog before it is started, the only state its period can be set in.

FwdgtRunning

The watchdog once it is counting down.

Wwdgt

The watchdog before it is started, the only state it can be configured in.

WwdgtRunning

The watchdog once it is counting down.

Enums

FwdgtPsc

Divider on IRC40K ahead of the counter (Table 12-1).

WwdgtPsc

Prescaler on the counter clock, named after the PSC field it writes.

Traits

FwdgtExt

Entry point on the raw peripheral.

WwdgtExt

Entry point on the raw peripheral.