gd32e2_hal/lib.rs
1//! Hardware abstraction layer for the `GD32E23x` series (Cortex-M23), built on top
2//! of the [`gd32e2`](https://crates.io/crates/gd32e2) peripheral access crate.
3//! Only the GD32E230 is implemented so far; the crate is named for the family it
4//! is meant to grow into.
5//!
6//! The API leans on the type system: a method that makes no sense for the
7//! hardware fails to compile.
8//!
9//! # Chip variants
10//!
11//! One feature names the part being built for, and exactly one must be enabled.
12//!
13//! A feature is the part number with an `x` in each field the code cannot see, so
14//! `gd32e230g8xx` is every G8 part: the letter is the bonded pin count (F 20, E 24,
15//! G 28, K 32, C 48), the digit the flash code (4 = 16K flash and 4K SRAM, 6 = 32K
16//! and 6K, 8 = 64K and 8K), and the last `x` the temperature grade. Only the 32-pin
17//! parts spell their package out — a QFN32 (`gd32e230k8ux`) carries VSS on its
18//! thermal pad and gives the two freed pins to `PB2` and `PB8`, an LQFP32
19//! (`gd32e230k8tx`) does not.
20//!
21//! # Getting started
22//!
23//! Clocks come first: freezing the tree is what produces the [`Rcu`](rcu::Rcu)
24//! every other module takes, and it enables each peripheral's clock as that
25//! peripheral is constructed.
26//!
27//! ```ignore
28//! let dp = pac::Peripherals::take().unwrap();
29//! let mut fmc = dp.fmc.constrain();
30//! let config = ClockConfig::default().sysclk(SysClk::Pll(PllFreq::Mhz48));
31//! let mut rcu = dp.rcu.constrain().freeze(&mut fmc, config);
32//! let parts = dp.gpioa.split(&mut rcu);
33//! let mut led = parts.pa5.into_output();
34//! led.set_high().unwrap();
35//! ```
36
37#![no_std]
38// --- Warnings ---
39#![warn(missing_docs)]
40// --- Cargo warnings ---
41#![warn(clippy::cargo)]
42#![allow(clippy::multiple_crate_versions)]
43// --- Pedantic warnings ---
44#![warn(clippy::pedantic)]
45#![allow(clippy::struct_field_names)]
46#![allow(clippy::cast_possible_truncation)]
47#![allow(clippy::cast_lossless)]
48#![allow(clippy::must_use_candidate)]
49// --- Unsafe warnings ---
50#![warn(clippy::undocumented_unsafe_blocks)]
51
52// Both halves of the choice are checked in build.rs, which counts the enabled
53// features and knows their names. This guards the source against being compiled
54// with no build script at all — the flags below are what every gate reads.
55#[cfg(not(any(chip_x4, chip_x6, chip_x8)))]
56compile_error!("select a chip: enable exactly one of the `gd32e230*` features");
57
58/// Re-export of the peripheral access crate this HAL is built on. Referring to
59/// it as `pac` keeps the door open to other parts of the family behind a single
60/// alias, instead of naming a specific chip module throughout.
61#[doc(no_inline)]
62pub use gd32e2::gd32e230 as pac;
63
64pub mod adc;
65pub mod cmp;
66pub mod crc;
67pub mod dma;
68pub mod exti;
69pub mod fmc;
70pub mod gpio;
71pub mod i2c;
72pub mod prelude;
73pub mod rcu;
74pub mod spi;
75pub mod syscfg;
76pub mod time;
77pub mod timer;
78pub mod usart;
79pub mod watchdog;