Module rcu 

Reset and clock unit: the system clock tree and per-peripheral clock gating.

RcuExt::constrain hands out an UnfrozenRcu, whose only method applies a ClockConfig and turns it into the Rcu every driver takes.

let mut fmc = dp.fmc.constrain();
let config = ClockConfig::default()
    .sysclk(SysClk::Pll(PllFreq::Mhz48))
    .adc_sel(AdcSel::Prescaled(AdcPsc::Apb2Div8));
let mut rcu = dp.rcu.constrain().freeze(&mut fmc, config);
let clocks = rcu.clocks();

Drivers switch their peripheral’s clock on themselves, through Enable.

HXTAL and LXTAL are never started.

Structs

ClockConfig

Builder for the clock tree, applied by freeze.

Clocks

Frozen clock frequencies, produced by UnfrozenRcu::freeze.

Rcu

Owns the RCU peripheral with its clock tree already frozen; obtained from UnfrozenRcu::freeze.

UnfrozenRcu

The RCU before its clock tree is frozen, handed out by RcuExt::constrain.

Enums

AdcPsc

Divider for the prescaled CK_ADC branch, including which bus it taps.

AdcSel

Source of the ADC clock.

AhbPsc

AHB prescaler: divides the system clock down to hclk.

ApbPsc

APB prescaler: divides hclk down to pclk1 (APB1) or pclk2 (APB2).

CkOutDiv

Divider applied to CK_OUT after the source multiplexer, for any source.

CkOutSrc

Clock node to route out on the CK_OUT pin.

Irc28mDiv

Divider on the internal 28 MHz oscillator feeding CK_ADC.

PllDiv

Divider on the PLL branch feeding CK_OUT, ahead of the source multiplexer.

PllFreq

Target system clock produced by the PLL, in 4 MHz steps up to the 72 MHz limit.

ResetFlag

What brought the chip up, as recorded in RSTSCK.

SysClk

Source of the system clock.

Usart0Sel

Source of the USART0 clock, independent of the APB2 bus clock.

Traits

Enable

Clock gating for a peripheral, implemented per peripheral type.

RcuExt

Extension trait turning the raw RCU peripheral into the managed UnfrozenRcu.

Reset

Reset control for a peripheral, implemented per peripheral type.