Expand description
I²C master.
7-bit addressing. Transactions are write, read and write_read (the
last joined by a repeated START), blocking or driven by interrupts; both
lines must be open-drain.
let sda = parts.pb7.into_alternate_open_drain::<1>();
let scl = parts.pb6.into_alternate_open_drain::<1>();
let mut i2c = I2c::new(&mut rcu, dp.i2c0, sda, scl, I2cMode::standard(100.kHz()));§Driving a transaction by hand
WriteTransfer and ReadTransfer are one way to do it; the primitives
they are built from are public, so a handler can be written instead. A
transaction is a sequence of phases, and the step a handler takes depends on
which one it is in.
Writing: write_start, then on
sbsend write_addr, then on
addsend clear_addsend, then one
write_byte per tbe. TBE stays up with
nothing left to feed, so unlisten(Event::Byte) after the last one and end
on btc with write_stop.
Reading is the same up to ADDSEND, and then turns on the acknowledge:
set_acken governs the byte already being clocked in, so
the NAK that ends the transaction has to be placed one byte early, and
set_poap moves it one further still. Both must stand
before the START. Four lengths behave differently: one byte NAKs before
ADDSEND is cleared; two ride on POAP and are taken together on BTC;
three go straight to that tail; longer ones take bytes on
rbne until three remain. Getting this wrong does not fail
loudly — the target keeps driving the line and the bus hangs.
Structs§
- I2c
- A configured I²C master, owning the peripheral and its two pins.
- Read
Transfer - A read driven by interrupts, owning the peripheral and the buffer.
- Write
Transfer - A write driven by interrupts, owning the peripheral and the buffer.
Enums§
- Duty
Cycle - Ratio of the low to the high half of an SCL period (
DTCY). - Error
- An error the peripheral flagged in
STAT0(manual Table 17-3). - Event
- An I²C event that can raise an interrupt.
- I2cMode
- Bus speed, and whatever else that speed implies.